三速以太网在SOPC里面是要使用SGDMA的。
SGDMA有两种模式，一个是Stream to Memory 一个是 Memory to Stream 。
生成的CPU与外部连接时要注意mdio引脚。
处理mdio的vhdl语句如下：
library ieee;
use ieee.std_logic_1164.all;
entity mdio is
port(m_oen:in std_logic;
m_out:in std_logic;
m_in:out std_logic;
mdio:inout std_logic);
end entity;
architecture art of mdio is
begin
mdio<=m_out when m_oen='0' else 'Z';
m_in<=mdio;
end art;
下面是Nios里面生成的关于Triple Speed Ethernet的文件：
<system.h>
#define ALTERA_ETHERNET_NAME "/dev/altera_ethernet"
#define ALTERA_ETHERNET_TYPE "triple_speed_ethernet"
#define ALTERA_ETHERNET_BASE 0x04001000
#define ALTERA_ETHERNET_SPAN 1024
#define ALTERA_ETHERNET_TRANSMIT "sgdma_to_str"
#define ALTERA_ETHERNET_RECEIVE "sgdma_to_mem"
#define ALTERA_ETHERNET_TRANSMIT_FIFO_DEPTH 2048
#define ALTERA_ETHERNET_RECEIVE_FIFO_DEPTH 2048
#define ALTERA_ETHERNET_FIFO_WIDTH 32
#define ALTERA_ETHERNET_ENABLE_MACLITE 1
#define ALTERA_ETHERNET_MACLITE_GIGE 1
#define ALTERA_ETHERNET_USE_MDIO 1
#define ALTERA_ETHERNET_IS_ETHERNET_MAC 1
#define ALT_MODULE_CLASS_altera_ethernet triple_speed_ethernet
/*下面是关于SGDMA的*/
#define SGDMA_TO_STR_NAME "/dev/sgdma_to_str"
#define SGDMA_TO_STR_TYPE "altera_avalon_sgdma"
#define SGDMA_TO_STR_BASE 0x04001400
#define SGDMA_TO_STR_SPAN 1024
#define SGDMA_TO_STR_IRQ 0
#define SGDMA_TO_STR_READ_BLOCK_DATA_WIDTH 32
#define SGDMA_TO_STR_WRITE_BLOCK_DATA_WIDTH 32
#define SGDMA_TO_STR_STREAM_DATA_WIDTH 32
#define SGDMA_TO_STR_ADDRESS_WIDTH 32
#define SGDMA_TO_STR_HAS_READ_BLOCK 1
#define SGDMA_TO_STR_HAS_WRITE_BLOCK 0
#define SGDMA_TO_STR_BURST_LENGTH 2
#define SGDMA_TO_STR_UNALIGNED_TRANSFER 0
#define SGDMA_TO_STR_CONTROL_SLAVE_DATA_WIDTH 32
#define SGDMA_TO_STR_CONTROL_SLAVE_ADDRESS_WIDTH 8
#define SGDMA_TO_STR_DESC_DATA_WIDTH 256
#define SGDMA_TO_STR_DESCRIPTOR_WRITEBACK_DATA_WIDTH 32
#define SGDMA_TO_STR_STATUS_TOKEN_DATA_WIDTH 24
#define SGDMA_TO_STR_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define SGDMA_TO_STR_BURST_DATA_WIDTH 8
#define SGDMA_TO_STR_CONTROL_DATA_WIDTH 8
#define SGDMA_TO_STR_STATUS_DATA_WIDTH 8
#define SGDMA_TO_STR_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define SGDMA_TO_STR_COMMAND_FIFO_DATA_WIDTH 104
#define SGDMA_TO_STR_SYMBOLS_PER_BEAT 4
#define SGDMA_TO_STR_IN_ERROR_WIDTH 0
#define SGDMA_TO_STR_OUT_ERROR_WIDTH 1
#define ALT_MODULE_CLASS_sgdma_to_str altera_avalon_sgdma
/*
* sgdma_to_mem configuration
*
*/
#define SGDMA_TO_MEM_NAME "/dev/sgdma_to_mem"
#define SGDMA_TO_MEM_TYPE "altera_avalon_sgdma"
#define SGDMA_TO_MEM_BASE 0x04001800
#define SGDMA_TO_MEM_SPAN 1024
#define SGDMA_TO_MEM_IRQ 1
#define SGDMA_TO_MEM_READ_BLOCK_DATA_WIDTH 32
#define SGDMA_TO_MEM_WRITE_BLOCK_DATA_WIDTH 32
#define SGDMA_TO_MEM_STREAM_DATA_WIDTH 32
#define SGDMA_TO_MEM_ADDRESS_WIDTH 32
#define SGDMA_TO_MEM_HAS_READ_BLOCK 0
#define SGDMA_TO_MEM_HAS_WRITE_BLOCK 1
#define SGDMA_TO_MEM_BURST_LENGTH 2
#define SGDMA_TO_MEM_UNALIGNED_TRANSFER 0
#define SGDMA_TO_MEM_CONTROL_SLAVE_DATA_WIDTH 32
#define SGDMA_TO_MEM_CONTROL_SLAVE_ADDRESS_WIDTH 8
#define SGDMA_TO_MEM_DESC_DATA_WIDTH 256
#define SGDMA_TO_MEM_DESCRIPTOR_WRITEBACK_DATA_WIDTH 32
#define SGDMA_TO_MEM_STATUS_TOKEN_DATA_WIDTH 24
#define SGDMA_TO_MEM_BYTES_TO_TRANSFER_DATA_WIDTH 16
#define SGDMA_TO_MEM_BURST_DATA_WIDTH 8
#define SGDMA_TO_MEM_CONTROL_DATA_WIDTH 8
#define SGDMA_TO_MEM_STATUS_DATA_WIDTH 8
#define SGDMA_TO_MEM_ATLANTIC_CHANNEL_DATA_WIDTH 4
#define SGDMA_TO_MEM_COMMAND_FIFO_DATA_WIDTH 104
#define SGDMA_TO_MEM_SYMBOLS_PER_BEAT 4
#define SGDMA_TO_MEM_IN_ERROR_WIDTH 6
#define SGDMA_TO_MEM_OUT_ERROR_WIDTH 0
#define ALT_MODULE_CLASS_sgdma_to_mem altera_avalon_sgdma
